Pulse: A New VHDL Simulator

With VHDL being probably more deterministic and bullet-proof than Verilog, it’s excellent to see another open source VHDL simulator signing up with the fray that is not a variation of ghdl. Written by [Óscar Grimal] in C++ with an MIT license, the Pulse project is a still in development plan that offers the whole toolchain, from the compiler to the requisite waveform output.

This waveform output is supplied in the kind of a text-based interface (TUI), which at the minimum assists a lot with making it cross-platform suitable. As reliances just a C++ 20 capable compiler and CMake are shown.

Of course, with VHDL being a rather substantial language particularly when you begin accumulating the involved basic library, the presently supported language and library functions are rather restricted still so that you’re restricted to fundamental IEEE plans and types, with default worths are not supported yet.

Per the roadmap on the GitHub task’s Readme more VHDL language functions consisting of generics and extra types will be included, together with a boosted simulation engine. It’s likewise stated that mixed-language assistance with Verilog will be included, though SystemVerilog seems getting the brief end of the stick as typical.

It will certainly be intriguing to compare this plan to ghdl.